The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a cell plate voltage generating apparatus thereof which freely provides a cell plate voltage at a desired level.
As developments in semiconductor technology lead to more compact semiconductor devices, the number of net dies increase, and as a result test time also increases. A multi-parallel test must therefore be performed in order to reduce the amount of test time.
A multi-parallel test method performs access to semiconductors simultaneously, and accordingly the multi-parallel test can reduce test time. However, the test equipment used in the multi-parallel test method must secure a number of channels that is equal to the number of channels of the semiconductor devices. However, a higher cost is associated with a large number of channels with regards to the test equipment. Accordingly, there is a desire to overcome a problem occurring when there is a lack of channels in test equipment, which is typically due to the high cost associated with large number of channels.
It is possible to conduct the multi-parallel test while reducing the number of internal voltage pins that require voltage monitoring (which may be a major cause of the lack of channels). A voltage monitor pad can be used to reduce the number of internal voltage pads.
FIG. 1 shows a block diagram of a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device includes: a voltage monitor pad VM; a monitor voltage selecting unit 10 which receives a test mode signal and a plurality of internal voltages and which selects one of the plurality of internal voltages and outputs the selected internal voltage to the voltage monitor pad; and a cell plate voltage generating unit 20 that generates a cell plate voltage in response to a test mode signal.
The monitor voltage selecting unit 10 comprises a decoding signal generating unit 12 and a transfer unit 14. The decoding signal generating unit 12 receives an enable signal EN_DEC, which enables the decoding signal generating unit 12, and a test mode signal TCM<0:2>. The decoding signal generating unit 12 outputs a decoding signal DEC<0:5> used for selecting one of the internal voltages by decoding the internal voltage signals. The transfer unit 14 receives a plurality of internal voltages VCP, VPP, VCORE, VBLP, VREFC, and VREFP and selects one of the internal voltages in response to the decoding signal DEC<0:5>. The transfer unit transfers the selected internal voltage to the voltage monitor pad VM.
The cell plate voltage generating unit 20 comprises: a pre cell plate voltage generating unit 22 that receives a test mode signal TVCP<0:3> and generates a pre cell plate voltage PREVCP in accordance with the test mode; and a driver 24 that receives the pre cell plate voltage PREVCP and amplifies and drives the pre cell plate voltage PREVCP to output the cell plate voltage VCP. The test mode signal TVCP<0:3> is a signal for changing the level of the pre cell plate voltage PREVCP.
FIG. 2 is a detailed circuit diagram showing the decoding signal generating unit 12 of FIG. 1. FIG. 3 is a detailed circuit diagram showing the transfer unit 14 of FIG. 1. Referring to FIG. 2 and FIG. 3, the decoding signal generating unit 12 generates control signals CTRL_DEC<0:2> using a plurality of NAND gates ND1, ND2, ND3 and a plurality of inverters INV1, INV2, INV3 in accordance with the enable signal EN_DEC and the test mode signal TCM<0:2>. The decoding signal generating unit 12 generates decoding signals DEC<0:5> using a plurality of NAND gates ND4 to ND9 and a plurality of inverters INV4 to INV9 in accordance with control signals CTRL_DEC<0:2>. The control signals CTRL_DEC<0:2> inputted to the NAND gates ND4 to ND9 enable only one decoding signal by combining the control signals CTRL_DEC<0:2> with inverted control signals CTRL_DECB<0:2> in a specific manner. For example, when the signals CTRL_DECB<0>, CTRLDECB<1>, CTRL_DECB<2> that are input to the NAND gate ND4 are each at a high level, the decoding signal DEC <0> is enabled and the remaining decoding signals DEC <1:5> are disabled. As such, only transfer gate TG0 (FIG. 3) is opened, and thus the cell plate voltage VCP is applied to the voltage monitor pad VM. Therefore, when using the test equipment it is possible to monitor the level of the cell plate voltage via the voltage monitor pad VM. The cell plate voltage VCP is generated and outputted by the cell plate voltage generating unit 20. However, the cell plate voltage VCP is inputted to the voltage monitor pad VM via the transfer gate TG0, and therefore the cell plate voltage's VCP drivability is decreased. Accordingly, the cell plate voltage generating unit 20 must have a level setting unit in order to change the level of the cell plate voltage. That is, when a level cell plate voltage is necessary, the level setting circuit, which changes the level of the cell plate voltage using the test mode signal, is separately required. Accordingly, the conventional circuit includes problems, in that the number of signal lines increases due to newly added test mode signals, and the addition of the level setting circuit leads to an increased layout area. Additionally, a test on levels not provided in the test mode is not possible.
FIG. 4 shows part of the conventional cell plate voltage generating unit 20 that includes a level setting circuit.
Referring to FIG. 4, the pre cell plate voltage generating unit 22 includes a level setting unit 26 for setting the level of the pre cell plate voltage, and a voltage dividing unit 28 that outputs the pre cell plate voltage PREVCP by dividing the voltage VCORE in accordance with the set level.
The level setting unit 26 includes a plurality of PMOS transistors PM0, PM1, PM2, PM3 each having an inverted test mode signal TVCP <0:3> supplied to the respective gate thereof. The voltage dividing unit 28 has a plurality of resistors R1, R2, R3, R4, R5, R6 connected in series. A node of each resistor is connected to a drain terminal of a respective one of PMOS transistors PM0, PM1, PM2, PM3 of the level setting unit 26. Therefore, it is possible to adjust the level of the pre cell plate voltage PREVCP by enabling the test mode signal TVCP <3> if a high voltage is required, and enabling the test mode signal TVCP <0> if a low voltage is required.
The pre cell plate voltage PREVCP generated as described above is amplified via the driver 24 and output as the cell plate voltage VCP. A current mirror may be included in the driver 24.
As described above, the conventional cell plate voltage is transferred to the voltage monitor pad using the transfer gate, and therefore the drivability of the cell plate voltage decreases, and thus a voltage level setting unit is required.